1. Field of the Invention
This invention relates generally to computer processors, and more specifically to processors that implement checkpointing.
2. Description of the Related Art
A modern processor may support taking one or more checkpoints, each of which may include saving an architectural state of the processor at a given time with respect to a program (or program thread) being executed. See, e.g., U.S. Pat. No. 7,571,304, which is incorporated by reference herein in its entirety. As but one example, a checkpoint might be taken by a processor that predicts an instruction stream to take one instruction path upon encountering a branch instruction (i.e., as opposed to taking another instruction path). Accordingly, upon determining that the branch has been mispredicted, execution could be rolled back to the checkpoint, including by using the saved architectural state associated with the checkpoint.
In certain processors, multiple checkpoints may be active at a given time, advantageously resulting in increased processor throughput. Supporting this ability to take multiple checkpoints, however, may require a non-trivial amount of processor real estate, particularly for processors that support a large number of architected registers.